1. Field of the Invention
The present invention relates to a semiconductor device and its fabrication method.
2. Description of the Related Art
Semiconductor devices having a substrate with through holes extending between the upper and lower surfaces to provide electrical connections therebetween have been proposed in, for example, Japanese Patent Application Publications No. 2003-318178 (pp. 1 to 5, FIGS. 1 to 8) and No. 2003-347502 (pp. 1 to 7, FIGS. 1 to 9).
The technology disclosed in the first of these Publications tapers the through holes in the depth direction. Consequently, if the through holes extend from the upper surface of the semiconductor device, where its functional components are formed, to the lower surface, the comparatively large openings on the upper surface reduce the space available for forming components. The circuit designer is therefore forced to use a semiconductor substrate with a comparatively large die size, making the semiconductor device comparatively expensive. If the through holes extend from the lower surface to the upper surface this problem can be avoided, but then the comparatively large openings of the holes on the lower surface come uncomfortably close to the edges of the lower surface, where cracks can easily form. If a crack propagates inward from an edge of the lower surface to a nearby through hole, the reliability of the through hole is impaired.
The technology disclosed in the second of the above Publications places the through holes in the peripheral areas of the semiconductor device, and angles the holes in a direction parallel to the adjacent edge of the device. There is consequently the same problem of proximity of the holes to the edges of the device on its lower surface and impaired reliability due to crack propagation from those edges to the through holes.